1. Field of Invention
The present invention relates to a buffer circuit. More particularly, the present invention relates to a mixed-voltage tolerant input/output (I/O) buffer in a semiconductor integrated circuit.
2. Description of Related Art
Integrated circuits (IC) are capable of being used nowadays to perform a wide variety of tasks. By packing many circuits onto the chip or integrating different circuits for different applications into one device, the total capabilities of the IC can be thus increased. Although the capabilities of the IC can be increased, different circuits may be operated at different voltages. For example, a system memory utilizes a voltage of 3.3 V and employs the same bus as the 5 V circuit, or the chip outputting an output voltage of 5V drives another chip powered by a power voltage of 1.8 V or 3.3 V. Therefore, a mixed-voltage tolerant I/O buffer is a necessary interface for communication between signals with different voltage levels.
However, the conventional mixed-voltage I/O buffer, which has an output stage circuit consisting of one PMOS transistor and one NMOS transistor or consisting of stacked NMOS transistors, is usually provided to transmit signals with limited voltage levels. If the mixed-voltage I/O buffer is going to be used as an interface to transmit the signal with a high voltage level (e.g. 2×VDD) or the signal with a low voltage level (e.g. 0.5×VDD), the output stage circuit will suffer from problems such as gate-oxide overstress, hot-carrier degradation and unpredictable leakage currents. As a result, the semiconductor device will have reliability problems.